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ICCD
2005
IEEE

Architectural Considerations for Energy Efficiency

13 years 16 days ago
Architectural Considerations for Energy Efficiency
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay and energy behaviors of gates and complex circuits due to supply scaling and circuit optimization on a modified test setup accounting for routing cost. The energy-throughput relationships of both pipelining and parallelism are characterized in connection to their corresponding depth and degree, showing clear advantages of pipelining over parallelism.
Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2005
Where ICCD
Authors Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
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