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2006
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Dynamic instruction schedulers in a 3-dimensional integration technology

12 years 11 months ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the critical path latency of a conventional dynamic scheduler is greatly affected by wire delay, we propose 3D-integrated scheduler designs by partitioning a conventional scheduler across multiple vertically-stacked die. The die-stacked organization reduces the lengths of critical wires thus reducing both latency and energy. Our simulation results show that a 20-entry (60-entry) instruction scheduler implemented in a 2-die stack achieves a 9% (15%) reduction in latency with simultaneous energy reduction as compared to a conventional planar design. The benefits are even larger when the instruction scheduler is implemented on a 4-die stack, with the corresponding latency reductions being 12% (22%). Categories and Subject Descriptors B.7 [Integrated Circuits]: Advanced technologies General Terms Design, Performance...
Kiran Puttaswamy, Gabriel H. Loh
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where GLVLSI
Authors Kiran Puttaswamy, Gabriel H. Loh
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