Memory Bank Predictors

13 years 16 days ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access can help to improve the performance in several ways. One scenario that is likely to become increasingly important is clustered microprocessors with a distributed cache. This work presents a study of different cache bank predictors. We show that effective bank predictors can be implemented with relatively low cost. For instance, a predictor of approximately 4 Kbytes is shown to achieve an average hit rate of 78% for SPECint2000 when used to predict accesses to an 8-bank cache memory in a contemporary superscalar processor. We also show how a predictor can be used to reduce the communication latency caused by memory accesses in a clustered microarchitecture with a distributed cache design.
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2005
Where ICCD
Authors Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González
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